1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic RAM (Random Access Memory) suitable for integration on a semiconductor substrate together with a logic circuit.
2. Description of the Background Art
Conventionally, logic circuits and dynamic RAMs (DRAM) of microprocessors and application specific integrated circuits (ASIC) have been produced as large scale integrated circuits (VLSI, ULSI, and the like) of high performance in accordance with increase of the integration density. These integrated circuits are produced respectively as individual chips, and connected to an external line on a system board in systems of personal computers.
It has become difficult to improve the high performance of the computer in such systems since the computing ability of the computer is restricted by the parasitic capacitance and resistance of the external wiring. Recently, an approach of improving the high performance has been effected by forming the logic circuit and the DRAM on the same semiconductor substrate.
Particularly, providing the metal wiring of the logic circuit in multilayers has been implemented. Development of multilayer metal wiring such as six or seven layers is in progress.
FIGS. 1A to 3B schematically show a fabrication process of a conventional semiconductor memory device having a DRAM formed of two metal interconnection layers and a logic circuit utilizing this DRAM embedded on the same semiconductor substrate. FIGS. 1A-3A correspond to the partial sectional views of the DRAM region whereas FIGS. 1B-3B correspond to the partial cross sectional views of the logic circuit region.
As shown in FIGS. 1A and 1B, following the formation of a field oxide film 2 for element isolation on an Si (silicon) substrate 1, a gate oxide film 3, a gate electrode 4 of a transistor of polycrystalline silicon, a word line (gate line) 4a, a silicon oxide film 5 thereon, and diffusion layers 6 and 6a are formed. An interlayer insulation film 217 is formed thereon by CVD. Then, an opening is formed at a portion of interlayer insulation film 217 for capacitor formation by a photoresist process and dry etching process.
As to the DRAM region, the process of thin film deposition, photoresist and dry etching is repeated to sequentially form a storage electrode 201 of the memory cell capacitor shown in FIG. 2A, a capacitor insulating film 202, and a cell plate electrode 203. Then, an interlayer insulating film 204 is formed thereon including the logic circuit region.
As to the same DRAM region, the above wiring and interlayer insulating film are deposited alternately and processed to form a bit line 206 constituted by a polycrystalline silicon film and a tungsten polycide film, and a contact hole 205 connecting bit line 206 with diffusion layer 6a. Then, an interlayer insulating film 207 is formed thereon including the logic circuit region.
In the above semiconductor memory device having a DRAM region and a logic circuit region embedded, a memory cell is formed of a memory cell transistor for address selection and a memory cell capacitor for data storage. The data storage operation is effected by storing charge in the memory cell capacitor. The amount of stored charge must be increased in order to read out data properly and speedily, and in order to lengthen the data retaining time.
The amount of charge stored in the memory cell capacitor of a DRAM is proportional to the voltage written into the memory cell. The write voltage of H (logical high) data is represented as below.
write voltage={xcex1Vccxe2x88x92(Vtn+xcex2)xc2x7xcex3}xe2x80x83xe2x80x83{circle around (1)}
Here,
xcex1: time function depending upon the time constant by the parasitic capacitance and resistance from the power supply voltage source up to the memory cell (xcex1xe2x89xa61)
xcex2: increase in threshold value depending upon back bias value
xcex3: coefficient depending upon write characteristics and operating cycle (xcex3xe2x89xa61)
Vcc: power supply voltage
Vtn: threshold of memory cell transistor
In such a DRAM, the write voltage can be increased by minimizing the second term (Vtn+xcex2) of equation {circle around (1)}. In general, the voltage of the word line is set higher than power supply voltage Vcc to cancel the minus of the second term.
In the case where the DRAM region and the logic circuit region are mounted together, it is desirable to form respective gate oxide films 3 of the logic circuit region and the DRAM region by the same step to simplify the oxide film formation step, as shown in FIGS. 1A to 3B. In this case, the thickness of respective gate oxide films 3 of the logic circuit region and the DRAM region becomes identical. From the standpoint of high speed, gate oxide film 3 of the logic circuit region is set relatively thin, so that gate oxide film 3 of the DRAM region is inevitably also thin. As a result, the voltage on the word line cannot be boosted since it is necessary to ensure the reliability of gate oxide film 3 of the DRAM region. This induces the problem that it is difficult to increase the write voltage, i.e. the amount of stored charge.
As an approach to solve this problem, Japanese Patent Laying-Open No. 10-134570 discloses the usage of a transistor having a threshold value lower than that of the general one (approximately 0.6 V) for the memory cell. Accordingly, the second term of the aforementioned equation {circle around (1)} can be reduced.
In this conventional art, the so-called shared sense amplifier system is employed. The sense amplifier is connected via the switching transistors disposed at both sides to the bit line pair arranged at both sides of the switching transistors. Accordingly, a write voltage is applied to the memory cell capacitor through a switching transistor and a memory cell transistor. In circuitry of such a structure, the voltage applied to the memory cell capacitor depends upon the threshold values of both the switching transistor and the memory cell transistor, and will be reduced by the threshold value of either of the two transistors that has the greater threshold value. When a memory cell transistor that has a low threshold value is employed, the threshold value of the switching transistor must also be of a similar low level.
However, reduction in the threshold value of the switching transistor necessitates the usage of a negative voltage Vbb as the voltage to reliably turn the transistor off. As a result, a circuit that drives in a wide operating range is required, causing the problem of a larger layout area. Furthermore, there is a problem that the load of the Vbb generation circuit becomes heavier to increase the circuit complexity and power consumption.
An object of the present invention is to provide a semiconductor memory device that has the write voltage of a memory cell capacitor increased.
According to an aspect of the present invention, a semiconductor memory device includes a first switching transistor for connecting a bit line extending from a memory sub array having a memory cell transistor to a first sense amplifier. The first switching transistor is arranged at a side opposite to the memory sub array than the input side of the sense amplifier.
In the semiconductor memory device of this aspect, the first sense amplifier includes a first P channel sense amplifier and an N channel sense amplifier. The first switching transistor is arranged between the first P channel sense amplifier and N channel sense amplifier to effect isolation and connection therebetween.
According to another aspect of the present invention, a semiconductor memory device includes a first common bit line, a second common bit line, an N channel sense amplifier, a first bit line, a second bit line, a first P channel sense amplifier, a first switching transistor, a second switching transistor, a third bit line, a fourth bit line, a second P channel sense amplifier, a third switching transistor, a fourth switching transistor, a word line, a memory cell capacitor, and a memory cell transistor. The second common bit line is complementary to the first common bit line. The N channel sense amplifier is connected between the first and second common bit lines. The second bit line is complementary to the first bit line. The first P channel sense amplifier is connected between the first and second bit lines. The first switching transistor is connected between the first common bit line and the first bit line. The second switching transistor is connected between the second common bit line and the second bit line. The fourth bit line is complementary to the third bit line. The second P channel sense amplifier is connected between the third and fourth bit lines. The third switching transistor is connected between the first common bit line and the third bit line. The fourth switching transistor is connected between the second common bit line and the fourth bit line. The memory cell transistor has a gate connected between the first bit line and the memory cell capacitor, and connected to a word line.
In this semiconductor memory device, the first P channel sense amplifier amplifies directly the voltage of the first or second bit line to the power supply voltage without the involvement of the first or second switching transistor. Therefore, the write voltage of the memory cell capacitor is increased to allow a larger storage capacity for the memory cell.
Preferably, the memory cell transistor has a threshold value lower than the threshold value of the first switching transistor. Accordingly, the storage capacity of the memory cell is further increased.
Preferably, the semiconductor memory device further includes an N channel drive transistor connected between a power supply node and the first P channel sense amplifier. Accordingly, the first P channel sense amplifier can apply a voltage lower than the power supply voltage by the threshold voltage of the N channel drive transistor to the first or second bit line.
According to another aspect of the present invention, a semiconductor memory device includes a semiconductor substrate, a dynamic random access memory formed on the semiconductor substrate, and a logic circuit formed on the semiconductor substrate to control the dynamic random access memory. A memory cell capacitor in the dynamic random access memory includes a capacitor insulating film of a thickness substantially identical to that of the gate insulating film of the transistor that forms the logic circuit. Accordingly, the capacitor insulating film of the memory cell capacitor can be formed in a step identical to that of the gate insulating film of the transistor that forms the logic circuit.
Preferably, the memory cell capacitor includes a cell plate electrode connected to ground. Therefore, a circuit to generate a cell plate voltage is not required.
According to a further aspect of the present invention, a semiconductor memory device includes a power supply line, a ground line, and a plurality of memory cell arrays. Each memory cell array includes a sub array having a plurality of bit line pairs, and a sense amplifier band adjacent to the sub array. The sense amplifier band includes a plurality of P channel sense amplifiers, a plurality of power supply drive transistors, a plurality of N channel sense amplifiers, and a plurality of ground drive transistors. The plurality of P channel sense amplifiers are connected to the plurality of bit line pairs, respectively. The plurality of power supply drive transistors are provided corresponding to the plurality of P channel sense amplifiers. Each power supply drive transistor is connected between the power supply line and a corresponding P channel sense amplifier. The plurality of N channel sense amplifiers are connected to the plurality of bit line pairs, respectively. The plurality of ground drive transistors are provided corresponding to the plurality of N channel sense amplifiers. Each ground drive transistor is connected between the ground line and a corresponding N channel sense amplifier.
The semiconductor memory device is advantageous in that the storage capacity can be easily increased by just designing repeatedly a memory cell array of the same structure.
According to still another aspect of the present invention, a semiconductor memory device includes a word line driver connected to a select signal line corresponding to a word line, and respectively supplying a voltage of the select signal line to a word line, a row address detection circuit responsive to a row address signal to selectively render the word line driver active, and a control circuit responsive to the row address signal to selectively supply a ground voltage or a negative voltage to the select signal line.
According to still another aspect of the present invention, a semiconductor memory device includes a plurality of word line drivers, a row address detection circuit and a control circuit. Each word line driver is connected to a plurality of word lines and a plurality of select signal lines corresponding to the plurality of word lines to supply the voltage on the plurality of select signal lines to the plurality of word lines, respectively. The row address detection circuit responds to a row address signal to selectively render the plurality of word line drivers active. The control circuit responds to a row address signal to selectively supply a ground voltage or a negative voltage to the plurality of select signal lines.
In this semiconductor memory device, a ground voltage or negative voltage is supply from the control circuit to a word line driver, whereby a word line is driven to the level of ground voltage or negative voltage. Therefore, power consumption of the circuit to generate a negative voltage can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.